Freescale Semiconductor /MK10F12 /SIM /SCGC5

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SCGC5

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)LPTIMER 0 (0)REGFILE 0 (0)TSI 0 (0)PORTA 0 (0)PORTB 0 (0)PORTC 0 (0)PORTD 0 (0)PORTE 0 (0)PORTF

PORTA=0, REGFILE=0, TSI=0, PORTC=0, PORTD=0, PORTB=0, PORTE=0, PORTF=0, LPTIMER=0

Description

System Clock Gating Control Register 5

Fields

LPTIMER

LPTMR clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.

REGFILE

Register File Clock Gate Control

0 (0): Clock is disabled.

1 (1): Clock is enabled.

TSI

TSI clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.

PORTA

PORTA clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.

PORTB

PORTB clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.

PORTC

PORTC clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.

PORTD

PORTD clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.

PORTE

PORTE clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.

PORTF

PORTF clock gate control

0 (0): Clock is disabled.

1 (1): Clock is enabled.

Links

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